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(中国科学院信息工程研究所, 北京 中国 100093;中国科学院大学, 北京 中国 100049)
FPGA平台上基于振荡环的物理不可克隆方法(Ring Oscillator based Physically Unclonable Function,以下简称RO PUF)以其简洁的架构和优良的属性而备受青睐。但是常用的RO PUF结构只能通过比较一对振荡环的频率,从两个振荡环里提取到1比特的熵。在很多应用中,尤其是基于PUF技术的密钥生成和随机数生成中,PUF响应能够保证提供足够的熵至关重要,为此,RO PUF需要部署大量的振荡环从而会消耗更多的资源。硬件资源利用率的低下极大限制了RO PUF的应用范围,尤其是资源受限的情景。针对这个问题,我们提出了一种简洁高效的方法,通过利用可编程延迟线(Programmable Delay Line,PDL)对延迟路径的精细控制,可以从每个振荡环中提取到相当于目前最优方案6倍的熵。我们将这种新型RO PUF结构命名为深度ROPUF (Further RO PUF)。本文不仅详细介绍了如何利用从实现振荡环的查找表(Look Up Table,LUT)中推导出的潜在随机变量,还展示更深层的制造差异变量是如何通过类似于高阶差分算法来提取的。除此之外,我们还建立了模型进行仿真并在XilinxVirtex-6和Zynq-7000系列评估板上进行了实验,通过展示仿真和实验结果的一致性来证明我们所提出方法的有效性和正确性。
关键词:  PUF  振荡环    高阶差分  可编程延迟线  FPGA
FROPUF: To Extract More Entropy from Two Ring Oscillators in FPGA-Based PUFs
LI Changting,ZHANG Qinglong,LIU Zongbin,JING Jiwu
Institute of Information Engineering, Chinese Academy of Sciences, Beijing 100093, China;University of Chinese Academy of Sciences, Beijing 100049, China
Ring Oscillator based Physically Unclonable Function (RO PUF) on FPGAs is popular for its nice properties and easy implementation. However, the conventional RO PUF only extracts 1-bit entropy by comparing two ROs' frequencies. For many applications, in particular for PUF-based key protection and random number generation, it is imperative that PUF responses provide sufficient entropy. In order to acquire adequate entropy, numerous ROs will be needed. RO PUF's inefficiency in hardware utilization constrains its application range, particularly in resource-constrained environments. Motivated by this inefficient resource usage, we propose an elegant and efficient method which can extract 6 times more entropy than the latest proposals by utilizing the fine control of Programmable Delay Lines (PDL). We call this construction Further ROPUF (FROPUF). In this paper, we present in detail how to take advantage of the underlying random process variation which derives from the Look Up Tables (LUT) of two ring oscillators, and show that the in-depth variation can be extracted by a high order difference calculation. In addition, we reveal the consistency of the evaluation results from Xilinx FPGAs (e.g. Virtex-6, Zynq-7000 65nm) and those by simulation of FROPUF, which confirms the effectiveness and correctness of the proposed method.
Key words:  PUF  Ring Oscillator  Entropy  High Order Difference  Programmable Delay Lines  FPGA